The present invention relates to a design support device of an LSI and a design method of an LSI, and can be utilized suitably in particular in determining a possibility of generation of a steady-state flow-through current from a power source to a ground.
A CMOS logic circuit is designed so that a circuit comprised of a P-type FET on a power supply side and a circuit comprised of an N-type FET on a ground side may not be set to an ON state concurrently, and a flow-through current does not flow in a steady state excluding a transient state as long as the outputs of plural logic gates are not short-circuited. On the other hand, some circuit is designed by employing a P-type FET and an N-type FET, intermingled with other CMOS logic circuits, without forming a CMOS logic circuit. One example of such a case is a circuit in which a pull-up and pull-down circuit and an analog circuit are intermingled with a CMOS logic circuit.
In such a circuit, there exists a possibility that a steady-state flow-through current may flow, in states where all the transistors in a path from a power source to a ground are set to ON, and where the output of a logic circuit which outputs LOW as a logical value is pulled up or conversely the output of a logic circuit which outputs HIGH as a logical value is pulled down. Such a state is brought about basically due to a design error; however, once such a circuit is made in a design phase, it is not easy to detect it by a simulation, etc.
Patent Literature 1 discloses a high impedance detecting method which can detect a flow-through current in a circuit by a simulation for an analog circuit including a transistor (refer to paragraphs 0031-0067). About a certain net in an integrated circuit, the disclosed technology extracts whether there exists the state in which a flow-through current is generated because of the net having high impedance and it also extracts that under what conditions a flow-through current is generated. Furthermore, the disclosed technology extracts whether there exists the state in which the net has high impedance, and also extracts that under what conditions the net becomes in the state of high impedance. When the extracted condition of the flow-through current and the extracted condition of the high impedance are both satisfied during the simulation execution, the flow-through current due to the high impedance is detected.
(Patent Literature)
    (Patent Literature 1) Published Japanese Unexamined Patent Application No. 2007-213456